Methods to form electronic devices and methods to form a material over a semiconductive substrate

ABSTRACT

A first electrode and a doped oxide layer laterally proximate thereof are provided over a substrate. A silicon nitride layer is formed over both the doped oxide layer and the first electrode to a thickness of no greater than 80 Angstroms over at least the first electrode by low pressure chemical vapor deposition using feed gases comprising a silicon hydride, H 2  and ammonia. The substrate with silicon nitride layer is exposed to oxidizing conditions comprising at least 700° C. to form a silicon dioxide layer over the silicon nitride layer, with the thickness of silicon nitride over the doped oxide layer being sufficient to shield oxidizable substrate material beneath the doped oxide layer from oxidizing during the exposing. A second electrode is formed over the silicon dioxide layer and the first electrode. In one implementation, the chemical vapor depositing comprises feed gases of a silicon hydride and ammonia, with the depositing comprising increasing internal reactor temperature from below 500° C. to a maximum deposition temperature above 600° C. and starting feed of the silicon hydride into the reactor at a temperature less than or equal to 600° C. In one implementation the depositing comprises increasing internal reactor temperature from below 500° C. to a maximum deposition temperature above 600° C. using a temperature ramp rate of at least 10° C./minute from at least 500° C. to at least 600° C. Other aspects and implementations are described.

TECHNICAL FIELD

This invention relates to methods to form electronic devices, forexample capacitors, antifuses, transistor gate and other constructions,and to methods to form a material over a semiconductive substrate.

BACKGROUND OF THE INVENTION

As the density of DRAM cells increases, there is a continuing challengeto maintain sufficiently high storage capacitance despite decreasingcell area. Additionally, there is a continuing goal to further decreasecell area. One principal way of increasing cell capacitance is throughcell structure techniques. Such techniques include three-dimensionalcell capacitors, such as trenched or stacked capacitors. Yet as featuresizes continue to become smaller and smaller, development of improvedmaterials for cell dielectrics as well as the cell design and structurebecome important. The feature size of higher density DRAMS, for example256 Mb, will be on the order of 0.25 micron and less. Such overallreduction in cell size drives the thickness of the capacitor dielectriclayer to smaller values, and conventional capacitor dielectric materialssuch as SiO₂ and Si₃N₄ might become unsuitable. However it would bedesirable to utilize silicon oxides and nitrides in spite of the reducedthicknesses due to the ease of use and available thorough understandingto integrate these materials in DRAM process flows. Yet processingassociated with chemical vapor deposition of thin silicon nitride filmsin certain environments has also created other problems not directlyassociated with the capacitors.

For example, one prior art technique is the fabrication of stackedcapacitors in a container shape within a borophosphosilicate glass layer(BPSG) to form the storage capacitors in DRAM circuitry. Here, acontainer opening is formed in a planarized layer of BPSG over a desirednode location, typically in the form of a conductive polysilicon plug.The conductive electrode material is deposited to less than completelyfill the opening, and then is typically chemical-mechanically polishedback to provide a storage node electrode inside of the BPSG opening inthe shape of a cup or container. Capacitor dielectric material is thenprovided over the storage node container, followed by deposition of aconductive cell plate layer which is subsequently patterned.

As circuitry integration and density increases, the correspondingdimensions and thicknesses of the various components also decreases. Atypical capacitor dielectric layer in the above construction comprises asilicon dioxide/silicon nitride/silicon dioxide composite (ONO). Thefirst oxide layer formed over the storage node electrode is typicallynative oxide formed by exposure of the exposed storage node material toambient air. Silicon nitride is next chemical vapor deposited, forexample utilizing a silicon hydride such as dichlorosilane and ammonia.Typical deposition conditions are at sub-Torr pressures and temperaturesat or above 680° C., more typically above 700° C. The deposition processand the very thin nature of the typically deposited silicon nitridelayer results in pin holes or other defects in the deposited layer. Thisis typically cured by a dense re-oxidation process which forms the outersilicon dioxide layer of the ONO construction. The prior artre-oxidation conditions for forming this outer oxide layer are conductedwet or dry at a temperature of from 800° C. to 950° C. at atmosphericpressure for from 5 to 30 minutes. Subsequently, a conductive cell platelayer is deposited and patterned over the ONO dielectric layer(s).

However as the nitride thickness of the ONO construction over thestorage node electrode fell to below 80 Angstroms, it was discoveredthat the underlying bulk silicon substrate was oxidizing to the point ofcircuit destruction. BPSG is known to be extremely diffusive tooxidizing components during the above-described re-oxidation conditions.Silicon nitride, on the other hand, is known to form a good barrierlayer to diffusion of such oxidizing gases under such conditions. Yet,the silicon nitride deposited over the BPSG in conjunction with thecapacitor dielectric layer formation was apparently inadequate inshielding oxidation of substrate material underlying the BPSG when thedeposited silicon nitride layer thickness for the capacitors fell below80 Angstroms.

The invention was principally motivated with respect to overcoming thisproblem to enable silicon nitride to continue to be utilized as acapacitor dielectric layer where its thickness fell to below 80Angstroms in deposition also occurring over a doped oxide layer, such asBPSG.

SUMMARY OF THE INVENTION

The invention comprises forming electronic devices, such as capacitors,antifuses, transistor gate and other constructions, and to methods offorming a material over a semiconductive substrate. In but oneimplementation, a first electrode and a doped oxide layer laterallyproximate thereof are provided over a substrate. A silicon nitride layeris formed over both the doped oxide layer and the first electrode to athickness of no greater than 80 Angstroms over at least the firstelectrode by low pressure chemical vapor deposition using feed gasescomprising a silicon hydride, H₂ and ammonia. The substrate with siliconnitride layer is exposed to oxidizing conditions comprising at least700° C. to form a silicon dioxide layer over the silicon nitride layer,with the thickness of silicon nitride over the doped oxide layer beingsufficient to shield oxidizable substrate material beneath the dopedoxide layer from oxidizing during the exposing. A second electrode isformed over the silicon dioxide layer and the first electrode.

In one implementation, the chemical vapor depositing comprises feedgases of a silicon hydride and ammonia, with the depositing comprisingincreasing internal reactor temperature from below 500° C. to a maximumdeposition temperature above 600° C. and starting feed of the siliconhydride into the reactor at a temperature less than or equal to 600° C.In one implementation the depositing comprises increasing internalreactor temperature from below 500° C. to a maximum depositiontemperature above 600° C. using a temperature ramp rate of at least 10°C./minute from at least 500° C. to at least 600° C. In preferredimplementations, the substrate is rotating during deposition, with thedepositing comprising increasing internal reactor temperature from below500° C. to a maximum deposition temperature above 600° C. and startingthe substrate to rotate prior to reaching the maximum depositiontemperature. In one implementation, rotation rate of the substrate isreduced upon substantially ceasing flow of at least one reactant gas tothe reactor. In one implementation, rotation rate of the substrate isreduced within 1 minute of substantially ceasing flow of the at leastone reactant gas to the reactor.

In one implementation, an inert cooling gas is flowed through a chemicalvapor deposition reactor to cool a substrate and deposited materialafter the deposition.

In one implementation, a doped oxide layer is provided over a substrate.The doped oxide layer is chemical-mechanical polished. After thechemical-mechanical polishing, the doped oxide layer is caused to flowin a process comprising at least two steps. A prior in time of the stepscomprises an inert atmosphere at a temperature of at least about 700° C.A later in time of the steps comprises an ammonia comprising atmosphereat a temperature of at least about 700° C. and forms a silicon nitridelayer over the doped oxide layer.

Other aspects and implementations are described below.

BRIEF DESCRIPTION OF THE DRAWINGS

Preferred embodiments of the invention are described below withreference to the following accompanying drawings.

FIG. 1 is a diagrammatic view of a semiconductor wafer fragment at oneprocessing step in accordance with the invention.

FIG. 2 is a view of the FIG. 1 wafer at a processing step subsequent tothat depicted by FIG. 1.

FIG. 3 is a view of the FIG. 1 wafer at a processing step subsequent tothat depicted by FIG. 2.

FIG. 4 is a view of the FIG. 1 wafer at a processing step subsequent tothat depicted by FIG. 3.

FIG. 5 is a view of the FIG. 1 wafer at a processing step subsequent tothat depicted by FIG. 4.

FIG. 6 is a diagrammatic depiction of a hot wall, vertical chemicalvapor deposition reactor usable in a process in accordance with theinvention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

This disclosure of the invention is submitted in furtherance of theconstitutional purposes of the U.S. Patent Laws “to promote the progressof science and useful arts” (Article 1, Section 8).

It has been recognized that the chemical vapor deposition of siliconnitride utilizing silicon hydride gases and ammonia occurs at differentrates over the storage node electrode of a DRAM capacitor (including anythin oxide formed thereover) and doped oxides. Specifically, suchdeposition of silicon nitride is largely selective to the storage node(typically polysilicon), and regardless is at a considerably greatergrowth rate than what occurs over the BPSG or other doped oxide layers.Accordingly, as the silicon nitride layer thickness over the storagenode fell to below 80 Angstroms, an apparent lesser quantity growingover the doped oxide layer resulted in a layer too thin to achieve thebarrier layer effect during the subsequent re-oxidation to form theouter oxide layer of the capacitor dielectric ONO composite. Severalprocessing solutions in accordance with the invention have beendeveloped.

Referring to FIG. 1, a semiconductor wafer fragment or substrate isindicated generally with reference numeral 10. To aid in interpretationof the claims that follow, the term “semiconductive substrate” isdefined to mean any construction comprising semiconductive material,including, but not limited to, bulk semiconductive materials such as asemiconductive wafer (either alone or in assemblies comprising othermaterials thereon), and semiconductive material layers (either alone orin assemblies comprising other materials). The term “substrate” refersto any supporting structure, including, but not limited to, thesemiconductive substrates described above.

Fragment 10 comprises a bulk monocrystalline silicon substrate 12 havinga diffusion region 14 formed therein. Field oxide region 16 and a gateoxide layer 18 are formed over bulk substrate 12. A pair of word lines20 and 22 are formed on opposing sides of diffusion region 14. Aconductive polysilicon plug 24 is provided over and in electricalconnection with diffusion region 14. A layer 26 of doped oxide,preferably BPSG, is provided over the illustrated component, and formedto have a container storage node opening 28 provided therein over plug24. A conductively doped, and preferably hemispherical grain,polysilicon layer has been formed over the substrate to within containeropening 28. Such has been planarized back to form the illustratedisolated first capacitor electrode 30, with doped oxide layer 26 beingpositioned laterally proximate thereof.

Referring to FIG. 2, a silicon dioxide layer 32 can be formed on firstcapacitor electrode 30, such as by exposing the substrate to ambient airto form a native oxide layer or by CVD or other deposition. Regardless,an exemplary thickness for layer 32 is 20 Angstroms. A silicon nitridelayer will subsequently be formed, as described below.

Referring to FIG. 3, a silicon nitride layer 34 is formed over bothdoped oxide layer 26 and first capacitor electrode 30 to a thickness ofno greater than 80 Angstroms over at least first capacitor electrode 30.Several aspects and implementations for forming layer 34 are possible asdescribed below. Various of the implementations could be utilized aloneor in any combination with other implementations as will be appreciatedby the artisan. Further, such can incorporate any of the methods andimplementations described in U.S. patent application Ser. No. ______ byRandhir P. S. Thakur, entitled “Methods of Forming Electronic Devices”and filed commensurate with the filing of this application, and which ishereby incorporated by reference.

Provision of layer 34 preferably comprises chemical vapor depositionusing feed gases comprising a silicon hydride and ammonia, and morepreferably low pressure chemical vapor deposition which is substantiallyvoid of plasma. In the context of this document, “low pressure chemicalvapor deposition” is intended to define any chemical vapor depositionprocess occurring at or below 700 Torr. Processing in accordance withthe above identified application filed on the same date as thisapplication, and in accordance with this application, is intended toresult in less selectivity of the deposition between exposed polysilicon(or thin oxide formed thereover) and undoped oxide of layer 26.Accordingly, a suitably thick layer 34 is intended to be deposited overthe doped oxide to effectively preclude oxidation of oxidizable materialbeneath layer 26 during a subsequent oxidation of the silicon nitridelayer. Layer 34 will also typically deposit to a thickness of less than80 Angstroms over doped oxide layer 26, and still perhaps to a thicknesslower than the thickness of the silicon nitride layer deposited overfirst capacitor electrode 30. Further, silicon nitride layer formationover first capacitor electrode 30 can be to a thickness of no greaterthan 60 Angstroms in accordance with a desired capacitor construction.

As shown, first capacitor electrode 30 is not outwardly exposed duringthe formation of silicon nitride layer 34 thereover, rather beingcovered by oxide layer 32. Alternately and perhaps more preferred, firstcapacitor electrode 30 is void of layer 32, and is outwardly exposedduring the formation of the silicon nitride layer 34 thereover, with thesilicon nitride layer being formed on doped first capacitor electrode30. Also as shown and preferred, the silicon nitride layer forms on thedoped oxide layer as opposed to on any intervening layer.

In but one implementation for depositing silicon nitride layer 34,internal reactor temperature is increased from below 500° C. to somemaximum deposition temperature above 600° C., with the starting of thefeed of the silicon hydride into the reactor occurring at sometemperature less than or equal to 600° C. Preferred pressure duringprocessing is from 1000 to 2000 Torr, with the preferred maximumdeposition temperature being 600° C. Typical prior art processingachieves a maximum deposition temperature of between 640° C. and 700°C., where ammonia flow is initially provided with the flow ofdichlorosilane and does not occur until maximum deposition temperatureis reached. Starting the feed of silicon hydride into the reactor at atemperature of less than or equal to about 600° C. in accordance with anaspect of the invention facilitates nitride layer deposition andreduction in the selectivity of such deposition relative to polysiliconor undoped oxide as compared to doped oxide layer 26. More preferably,feed of the silicon hydride into the reactor is started at a temperatureof less than or equal to 550° C., with less than or equal to 500° C.being even more preferred. Ammonia feed to the reactor also preferablyoccurs at a temperature of less than or equal to 600° C. The temperaturethen preferably ramps continuously upward to achieve the maximumdeposition temperature.

In one implementation, the depositing comprises increasing internalreactor temperature from below 500° C. to a maximum depositiontemperature above 600° C. using a temperature ramp rate of greater than10° C./min from at least 500° C. to at least 600° C. The temperatureramp rate is preferably no greater than 100° C./min from at least 500°C. to at least 600° C. Preferably, the temperature ramp rate of greaterthan 10° C./min starts from a temperature below 500° C. and continues toa temperature above 600° C., and more preferably continues untilreaching the maximum deposition temperature. Prior art processingachieves a temperature ramp rate up to the maximum depositiontemperature of between 8° C. to 10° C. per minute. Increasing the ramprate above 10° C. achieves an unexpected result of less selectivity inthe silicon nitride layer deposition, and achieving better radialuniformity across a wafer surface during the deposition.

In another implementation, the substrate is rotating during depositionand is started to rotate prior to reaching a maximum depositiontemperature above 600° C. Preferably, the substrate is started to rotateprior to the reactor temperature reaching 600° C., and upon commencinginitial feed of the silicon hydride to the reactor at below 600° C. Apreferred wafer rotation speed is from 5 to 10 rpm. In the prior artdeposition, wafer rotation wasn't commenced until achieving a maximumdeposition temperature of at least 640° C. and immediately prior to orcommensurate with reactant gas injection. Commencing rotation inaccordance with this implementation of the invention achieves lessselectivity in the deposition and more radial uniformity in thedeposition across the substrate.

In another implementation, rotation rate of the substrate is reducedupon substantially ceasing flow of at least one of the silicon hydrideand ammonia to the reactor at the substantial conclusion of thedeposition. An example rotation rate range during depositing and after aspeed reduction is from about 3 rpm to 15 rpm. The rotation rate ispreferably reduced by at least 50% to 70% of that rate immediately priorto substantially ceasing flow of the at least one of the silicon hydrideand ammonia to the reactor. Also preferably, the reducing is to someconstant layer rate which is maintained for at least 1 to 2 minutes,such as during initial wafer cooling. The rotation rate is preferablyreduced upon substantially ceasing flow of the silicon hydride to thereactor, which is also preferably commensurate with ceasing flow of theammonia to the reactor.

In one implementation, rotation rate of the substrate is reduced within1-2 minutes of substantially ceasing flow of at least one of the siliconhydride and ammonia to the reactor. More preferably, such rotationreduction occurs within 30 to 60 seconds of the flow stoppage. Reducingcan occur before or after substantially ceasing flow of at least one ofthe reactant gases, and preferably occurs upon/commensurate with ceasingflow of at least one of the reactant gases as described above. The prioris understood to maintain a constant rotation rate of about 5 rpm uponreaching maximum deposition temperature and continuing such rate afterceasing flow of the reactant gases and throughout cooling of the wafers.Processing in accordance with the immediately above-described preferredimplementations has the effect of improving the radial uniformity acrossthe wafer during deposition. Rotation facilitates control of depletionof the reactant species across the wafer and across the load.

In accordance with another implementation, low pressure chemical vapordeposition of layer 34 utilizes feed gases comprising a silicon hydride,H₂ and ammonia. The H₂ is preferably injected to within the reactorduring the deposition as an N₂/H₂ mix. The H₂ is preferably added inaddition to existing preferred flows of ammonia and silane at apreferred 3:1 or greater volumetric ratio. The prior art has notprovided a separate feed of H₂ gas to the reactor. Provision of such inaccordance with this implementation achieves less selectivity in thesilicon nitride layer deposition and more radial uniformity in thedeposition across the wafer.

A further considered deposition process for layer 35 is described withreference to FIG. 6. This depicts a vertical, hot wall chemical vapordeposition reactor 50 having a plurality of substrates 10 orientedhorizontally therein. Chemical vapor depositing in accordance with thisaspect of the invention comprises injecting silicon hydride to withinthe if reactor at multiple spaced locations 52, positioned proximatespaced wafers of the plurality of wafers being deposited upon. Ammoniaand H₂ can also be injected from multiple locations, but are preferablyinjected to within the reactor at only single respective locations, asshown. The prior art processing and provision of dichlorosilane to thereactor in conjunction with the silicon nitride layer deposition havingthe problems to which this invention is directed to overcoming onlyprovides silane injection at/from a single location at the bottom of thereactor. Provision of the less mobile silicon hydride from multiplespaced locations positioned proximate spaced wafers within the reactorhas the effect of achieving less selectivity in the nitride layerdeposition, and potentially more radial uniformity in the depositionacross the wafer.

In accordance with another implementation, the doped oxide layer iscaused to flow in a process comprising at least two steps. The flowingis preferably conducted after all chemical-mechanical polishing or otherremoval processes has occurred relative to the outermost surface oflayer 26. A prior in time of the flowing steps comprises an inertatmosphere at a temperature of at least about 700° C. Preferredconditions are flowing N₂ and/or Ar at a temperature of from about 950°C. to 1050° C. at atmospheric pressure for from about 10 to 30 seconds.A later in time of the steps comprises feeding ammonia at a temperatureof at least 700° C. which forms a silicon nitride layer at least overdoped oxide layer 26. Preferred temperature, pressure and time ofprocessing conditions are as immediately described above with respect tothe inert atmosphere. Such flow/reflow processing in accordance with theinvention will either form a suitably thick silicon nitride layer topreclude oxidation of substrate material beneath oxide layer 26 duringlater processing, or at least form a suitably thick initiating seedlayer for achieving a suitably thick silicon nitride layer by subsequentdeposition for complete fabrication of silicon nitride layer 34. Flowingof doped oxide layer 26 might also be conducted prior tochemical-mechanical polishing or any other planarizing of the outersurface thereof.

In accordance with another implementation and at the conclusion of thedeposition, an inert cooling gas is flowed through the reactor to coolthe substrate and deposited material. Preferably, pressure within thereactor during such cooling is greater than one atmosphere. Prior artprocesses for cooling the wafers flow cooling gas externally of thereactor to cool the reactor walls, which ultimately results in wafercooling. Flowing an inert cooling gas directly through the reactor tocool the substrate and deposited silicon nitride layer achieves moreradial uniformity in such layer across the wafer.

Referring again to FIG. 4, the substrate is exposed to oxidizingconditions comprising at least 700° C. to form a silicon dioxidecomprising layer 36 over silicon nitride layer 34. The thickness ofsilicon nitride layer 34 over doped oxide layer 26 is sufficient toshield oxidizable substrate material beneath doped oxide layer 26 (i.e.,bulk substrate material 12) from oxidizing during the re-oxidationexposure. An example and preferred thickness for layer 36 is from 10 to15 Angstroms on the nitride surface. Example wet oxidation conditions(i.e., in the presence of steam) or dry oxidation conditions (i.e., inthe presence of oxygen) include exposure at from 800° C.-950° C. in anatmospheric furnace for from 5 to 30 minutes.

Referring to FIG. 5, a second capacitor electrode layer 38 (i.e.,conductively doped polysilicon) is deposited and patterned to form asecond capacitor electrode over silicon dioxide layer 36 and firstcapacitor electrode 30. Such provides but one example method inaccordance with the invention for producing an adequately thick layer ofsilicon nitride over BPSG layer 26 in spite of thickness of such layerat least over storage node layer 30 being less than 80 Angstroms thick.

Again, the invention was principally motivated from problems associatedwith capacitor fabrication where silicon nitride layer thickness in anONO construction fell below 80 Angstroms, with the substrate alsocomprising outwardly exposed boron and/or phosphorus doped silicateglass. Aspects of the invention are also believed applicable infabrication of other electronic devices and materials, with theinvention only being limited by the accompanying claims appropriatelyinterpreted in accordance with the Doctrine of Equivalents. By way ofexample only, example alternate constructions include antifuses andtransistor gates. For example, the invention contemplates fabrication ofsilicon nitride layers, such as described above, to comprise at least aportion of a dielectric layer separating two antifuse electrodes.Further, methods in accordance with the invention could also be utilizedto fabricate gate dielectric layers, such as layer 18 of the FIG. 1-13above-described embodiments. Further, the invention contemplatesprocessing of dielectric layers in the context of floating gatefabrication, with the subject dielectric layer forming either thetypical top and/or bottom dielectric layer(s) utilized in floating gateconstructions.

Further, the invention contemplates methods of forming electronicdevices incorporating a high K dielectric layer construction. In thecontext of this document, “high K” is intended to define a dielectriclayer having a dielectric constant K of at least 15. By way of exampleonly, such materials include (Ba, Sr)TiO₃, SrTiO₃, (Pb, Zr)TiO₃, Ta₂O₅,and Nb₂O₅. Nitride layers formed in accordance with the invention, suchas described above, can form useful passivation and other purpose layerswhen formed on high K dielectric layers utilized in electronic devicesincorporating high K dielectric layers and another conductive component,such as for example capacitors in antifuse constructions.

Aspects of the invention are also contemplated outside of formation ofelectronic devices as described in the preferred embodiments above.Specifically, reducing rotation rate of the substrate upon substantiallyceasing flow of one reactant gas into the reactor, or within 1 to 2minutes of doing so, is usable in formation of various materials oversemiconductor substrates by chemical vapor deposition. The same is alsoapplicable to flowing of an inert cooling gas through the chemical vapordeposition reactor at the conclusion of deposition. Further, doped oxideflow or reflow in a layer comprising at least two steps as describedabove and claimed after chemical-mechanical-polishing is alsocontemplated outside of fabrication of an electronic device comprisingtwo conductive electrodes having a silicon nitride layer positionedtherebetween.

In compliance with the statute, the invention has been described inlanguage more or less specific as to structural and methodical features.It is to be understood, however, that the invention is not limited tothe specific features shown and described, since the means hereindisclosed comprise preferred forms of putting the invention into effect.The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrine ofequivalents.

1-53. (canceled)
 54. A method of forming an electronic devicecomprising: providing a first electrode and a doped oxide layerlaterally proximate thereof over a substrate; low pressure chemicalvapor depositing a silicon nitride layer over both the doped oxide layerand the first electrode to a thickness of no greater than 80 Angstromsover at least the first electrode using feed gases comprising a siliconhydride and ammonia within a reactor while the substrate is rotating;reducing rotation rate of the substrate upon substantially ceasing flowof at least one of the silicon hydride and ammonia to the reactor;exposing the substrate with silicon nitride layer to oxidizingconditions comprising at least 700° C. to form a silicon dioxide layerover the silicon nitride layer, with the thickness of silicon nitrideover the doped oxide layer being sufficient to shield oxidizablesubstrate material beneath the doped oxide layer from oxidizing duringthe exposing; and forming a second electrode over the silicon dioxidelayer and the first electrode.
 55. The method of claim 54 wherein therotation rate is reduced by at least 50% of that immediately prior tosubstantially ceasing flow of the at least one of the silicon hydrideand ammonia to the reactor.
 56. The method of claim 54 wherein saidreducing is to some constant lower rate which is maintained for at least1 minute.
 57. The method of claim 54 wherein rotation rate is reducedupon substantially ceasing flow of the silicon hydride to the reactor.58. The method of claim 54 wherein rotation rate is reduced uponsubstantially ceasing flow of the ammonia to the reactor.
 59. The methodof claim 54 wherein flow of the silicon hydride and ammonia is ceased atsubstantially the same time. 60-68. (canceled)
 69. A method of formingan electronic device comprising: providing a first electrode and a dopedoxide layer laterally proximate thereof over a substrate; low pressurechemical vapor depositing a silicon nitride layer over both the dopedoxide layer and the first electrode to a thickness of no greater than 80Angstroms over at least the first electrode using feed gases comprisinga silicon hydride and ammonia within a reactor while the substrate isrotating; reducing rotation rate of the substrate within 2 minutes ofsubstantially ceasing flow of at least one of the silicon hydride andammonia to the reactor; exposing the substrate with silicon nitridelayer to oxidizing conditions comprising at least 700° C. to form asilicon dioxide layer over the silicon nitride layer, with the thicknessof silicon nitride over the doped oxide-layer being sufficient to shieldoxidizable substrate material beneath the doped oxide layer fromoxidizing during the exposing; and forming a second electrode over thesilicon dioxide layer and the first electrode.
 70. The method of claim69 wherein the reducing occurs within 60 seconds of substantiallyceasing flow of the at least one of the silicon hydride and ammonia tothe reactor.
 71. The method of claim 69 wherein the reducing occurscommensurate with or after substantially ceasing flow of the at leastone of the silicon hydride and the ammonia to the reactor.
 72. Themethod of claim 69 wherein the reducing occurs after substantiallyceasing flow of the at least one of the silicon hydride and the ammoniato the reactor.
 73. The method of claim 69 wherein the reducing occursbefore substantially ceasing flow of the at least one of the siliconhydride and the ammonia to the reactor.
 74. The method of claim 69wherein the rotation rate is reduced by at least 50% of that immediatelyprior to starting said reducing.
 75. The method of claim 69 wherein saidreducing is to some constant lower rate which is maintained for at least1 minute.
 76. The method of claim 69 wherein the reducing occurscommensurate with or after substantially ceasing flow of the at leastone of the silicon hydride and the ammonia to the reactor, and thereducing is to some constant lower rate which is maintained for at least1 minute. 77-80. (canceled)
 81. A method of forming an electronic devicecomprising: providing a first electrode and a doped oxide layerlaterally proximate thereof over a substrate; low pressure chemicalvapor depositing a silicon nitride layer over both the doped oxide layerand the first electrode to a thickness of no greater than 80 Angstromsover at least the first electrode using feed gases comprising a siliconhydride and ammonia within a reactor; after the depositing, flowing aninert cooling gas through the reactor to cool the substrate anddeposited material; after the cooling, exposing the substrate withsilicon nitride layer to oxidizing conditions comprising at least 700°C. to form a silicon dioxide layer over the silicon nitride layer, withthe thickness of silicon nitride over the doped oxide layer beingsufficient to shield oxidizable substrate material beneath the dopedoxide layer from oxidizing during the exposing; and forming a secondelectrode over the silicon dioxide layer and the first electrode. 82.The method of claim 81 wherein pressure within the reactor during thecooling is greater than 1 atmosphere.
 83. A method of forming anelectronic device comprising: providing a doped oxide layer over asubstrate; chemical-mechanical polishing the doped oxide layer; andafter the chemical-mechanical polishing, flowing the doped oxide layerin a process comprising at least two steps, a prior in time of the stepscomprising an inert atmosphere at a temperature of at least about 700°C., a later in time of the steps comprising an ammonia comprisingatmosphere at a temperature of at least about 700° C. and forming asilicon nitride layer over the doped oxide layer.
 84. The method ofclaim 83 comprising flowing the doped oxide layer prior to thechemical-mechanical polishing at a temperature of at least about 700° C.85. The method of claim 83 wherein the doped oxide comprises phosphorousdoped glass.
 86. The method of claim 83 wherein the doped oxidecomprises boron doped glass.
 87. The method of claim 83 wherein thedoped oxide comprises boron and phosphorous doped glass.
 88. A method offorming an electronic device comprising: providing a doped oxide layerover a substrate; forming an opening into the doped oxide layer;depositing conductive material to less than completely fill the openingand form over the doped oxide layer proximate the opening; removing theconductive material formed over the doped oxide layer proximate theopening to isolate the conductive material within the opening; after theremoving, flowing the doped oxide layer in a process comprising at leasttwo steps, a prior in time of the steps comprising an inert atmosphereat a temperature of at least about 700° C., a later in time of the stepscomprising an ammonia comprising atmosphere at a temperature of at leastabout 700° C. and forming a silicon nitride layer at least over thedoped oxide layer; exposing the substrate with silicon nitride layer tooxidizing conditions comprising at least 700° C. to form a silicondioxide layer over the silicon nitride layer and the conductivematerial, with the thickness of silicon nitride over the doped oxidelayer being sufficient to shield oxidizable substrate material beneaththe doped oxide layer from oxidizing during the exposing; and forming aconductive electrode over the silicon dioxide layer and the conductivematerial.
 89. The method of claim 88 comprising flowing the doped oxidelayer prior to the chemical-mechanical polishing at a temperature of atleast about 700° C.